Execution of Instructions

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I’m reading a book on Introduction to Computer Architecture.

One excerpt from the book says the following about the RISC interface of processors: "Each instruction typically takes a clock cycle."

But the same book contains the following illustrative excerpt, in Verilog language:

always @(positiveclockedge clk )
begin
    case ( state )
        STATE_FETCH:
            begin
              fetch;
              state = STATE_DECODE;
            end
        STATE_DECODE:
            begin
                decode;
                state = STATE_EXECUTE;
            end
        STATE_EXCUTE:
            begin
                execute;
                state = STATE_FETCH;
            end
    endcase
end

According to the Verilog excerpt, even RISC processors take at least 3 clock cycles for an instruction (ignoring any memory access delay). Someone can give me a light in this matter, since there is an apparent contradiction (I have noticed this in other texts I have read)?

assembly architecture-computers

  • "Each instruction typically takes a clock cycle", presumably means "the run stage" is done in a clock cycle. I think the assumption is right. Source: Stackoverflow in English.

2 answers

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Usually processors do not execute an entire instruction in a single clock cycle. But at the same time they run one instruction per clock cycle. How is that possible? Pipeline!

inserir a descrição da imagem aqui

As you can see from the graph, on average an instruction has just been executed at each clock cycle, generating the fallacy of 1 instruction = 1 cycle.

In each cycle 4 instructions can be executed simultaneously. This, of course, in a processor that divides the pipeline into 4 parts, can be a different amount. And that’s why it’s so important that the processor can predict what the next instruction will be before it even finishes the current instruction (See more details about Branch Prediction).

This division of tasks into parts enables faster processors with reduced clock time. The difficulty appears in trying to make sure that subsequent instructions are valid and can be executed in this way. If for example an instruction writes to the register and the following statement reads from that register, we have a conflict, we cannot run "parallel" in the pipeline. Some processors are able to even reorder instructions to minimize waiting times.

  • Pedagogically such types of assertion are confusing, especially for beginners. When one says "generating the fallacy 1 instruction = 1 click" one is notoriously talking about time, but not how many cycles were necessary for the execution of the instruction. My big problem was having to deal with this ambiguity as a beginner on the subject. Anyway, it was very good the clarification. " Branch Prediction" is a more advanced subject.

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