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I’ve been exploring VHDL and I have a problem I haven’t been able to solve.
I have several inputs (data outputs from different Fifos) that are ready to be sent at the same time. These inputs are outputs of several Fifos, as shown in the following image. 
These inputs want to access the same bus (represented by the blue block) at the same time. How can I activate the read_en of each FIFO, to pass each dataout to the bus, without losing data, and at different times?
I know that data1 is ready to read (activate rd_en1) when data1 (15) = '1' (MSB) and is finished when data1 (15) = '0', and the same applies to the rest of FIFOS. Should I try to solve with a FSM (Finite State Machine)? (I have tried and failed) , if anyone has any idea how to solve this problem I would appreciate.
Thank you very much !