LR register with zero value in IRQ Interruption Handler

Question

Configuration of the interrupt vector:

interruption vector:
        b RESET_HANDLER
    .org 0x08
        b SVC_HANDLER
    .org 0x18
        b IRQ_HANDLER

In the first line of routine IRQ_HANDLER, the value of the registrant LR (visa with the aid of GDB) is 0.

As a consequence, at the end of the routine subs pc, lr, #4 result is an error of type Segmentation Fault.

Any hint?

Answer 1

The routine subs pc, lr, #4 arrow to the recorder PC the value of the recorder LR (which as mentioned is zero) minus the immediate #4 that is, in the next cycle the processor should summarize the execution from LR - 4 which is an invalid address, so the SEGFAULT.

Steps to be taken to safely enable interruptions IRQ described in ARM documentation sane:

1. Build the return address and save it to the mode stack IRQ.
2. Save the required registers and the SPSR in the way IRQ.
3. Identify and clear source of interruption.
4. Switch to mode System keeping the IRQs disabled.
5. Check that the stack is aligned to eight bytes and adjust if necessary.
6. Save the LR in the way User and the adjustment, 0 or 4 for ARMv4 or ARMv5TE, used in the SP in the way User.
7. Enable interruptions and call interrupt handler function.
8. When the handler function returns, disable interruptions.
9. Restore the LR in the way User and the stack setting value.
10. Reset the battery if necessary.
11. Switch to mode IRQ.
12. Restore the other registers and the SPSR in the way IRQ.
13. Return from IRQ.

In short: make sure you’re using the value of LR in the right way and that is not overwriting anywhere.

Important: The return of an interruption is different of the return of a function because the PC saves the address of the next instruction to be executed and in an exception/interruption the value of PC is copied to LR_<mode> then if you jumped to that value the instruction referenced by this address would never be executed, so that’s the subtraction (LR - 4).