Makefile compile all files. c without specifying them

Question

I’m trying to create a Makefile that makes all the files .c be compiled without me having to add the files line by line in the Makefile. I tried to keep up with the Creating a Makefile, but I found it very confusing. My interest is the same:

1 - Check all files .c possess their equivalents .o;

2 - Not possessing the .o, create it from the file name .c, before checking your headers files .h.

My current Makefile:

BIN     = ./bin
OBJ     = ./obj
INCLUDE = ./include
SRC     = ./src

all:
    gcc -c "$(SRC)/Distancias.c" -o "$(OBJ)/Distancias.o"
    gcc -c "$(SRC)/ManipulaVetores.c" -o "$(OBJ)/ManipulaVetores.o"
    gcc -c "$(SRC)/Classificador.c" -o "$(OBJ)/Classificador.o"
    gcc -c "$(SRC)/ManipulaArquivos.c" -o "$(OBJ)/ManipulaArquivos.o"
    gcc -c testes.c -o "$(OBJ)/main.o"
    gcc -o $(BIN)/main.exe $(OBJ)/*.o -lm

run:
    $(BIN)/main.exe

clean:
    del /F /Q "$(OBJ)" ".o"
    del /F /Q "$(BIN)" ".exe"

I’d like to do something like $(SRC)/*.c, but I know it’s not that simple because that way it’s not possible to name the .o.

As to the clean, I’ve looked for all kinds of commands and I haven’t found a way to make it work on different platforms. As I am on Windows, I am using the del.

Answer 1

Reference

Testing.

zv@localhost test-make]$ ll
total 16
-rw-rw-r--. 1 zv zv  70 nov  3 10:19 func1.c
-rw-rw-r--. 1 zv zv  70 nov  3 10:20 func2.c
-rw-rw-r--. 1 zv zv 277 nov  3 10:15 main.c
-rw-rw-r--. 1 zv zv  40 nov  3 10:24 Makefile

[zv@localhost test-make]$ cat Makefile 
test: $(wildcard *.c)
      $(CC) -o $@ $^

[zv@localhost test-make]$ make
cc -o test func1.c main.c func2.c

[zv@localhost test-make]$ ./test 
*
* calling func1
* in func1
* called func1
*
* calling func2
* in func2
* called func2
*
[zv@localhost test-make]$