Why can’t all if have Isis?

Question

I’m exploring a little about FPGA and wanted to do something very simple, a button that when clicked would change the status.

Ignoring the other problems in logic itself, the fact that caught my attention was that it didn’t even "compile":

if rising_edge(clk) then
   status <= '1';
else 
   status <= '0';
end if;

It returns me an error:

[Synth 8-27] Else clause after check for clock not supported

In addition to two other errors:

[Synth 8-285] failed synthesizing module 'out'
[Common 17-69] Command failed: Synthesis failed - Please see the console or run log file for Details

I’m using a Xilinx Artix-7, using Vivado 2017.1, if this is something important.

---

That’s totally weird, I’ve always assumed that if could have a else, but it seems that not so.

Why does this happen? And under what other conditions else cannot be used?

Answer 1

There are some additional complicators in the matter of "reading" a button that will interfere with the outcome, especially the deboucing to eliminate mechanical noises from the button, but I will not go into these details in the answer.

For more information: Debounce Logic Circuit (with VHDL example)

As I commented, this strangeness is caused whenever you try to analyze the VHDL code as a program and not as an electronic circuit (reason why I stated in my reply that VHDL should not be considered programming language). Do the code snippet below:

if rising_edge(clk) then
    status <= '1';
else
     status <= '0';
end if;

It doesn’t make much sense when you analyze the circuitry it should generate. Basically the code is saying: the signal status must receive the value '1' whenever there is a positive transition in the signal clk and in all other cases should receive '0'. When the signal clk stabilizes in '1' after the transition will already characterize a another case, entering the else; that is, ideally the signal transition time is 0, then the signal status would be at the high logical level for a time equal to 0. The synthesizer cannot understand this and generates the error.

To make visualization easier, we can actually draw the circuit. When you want to change the state of a signal based on changing the state of another signal you will be working with registers. That is, the part of if would generate the following circuit:

That it is nothing more than a register that assigns the value '1' at the sign status where there is a positive transition clk. Realize that there is no way to generate a circuit that is the negation of expression rising_edge to generate the else, and whereas the duration of the value '1' would be 0 in this situation, it would be equal to '0' whenever, what would generate the circuit:

Which makes no sense, because the signal status would receive two different values, '1' and '0', in every positive transition of clk.

But it is interesting to note that this occurs mainly when you are dealing with the transitions in if. If you only treat the value, usually the synthesizer will understand what you want to do and synthesize the appropriate circuit. An example very simple of a button would be to verify, each positive transition of the clk, if the logic level of the button is 0¹ and, when it is, set the value of status for '1'.

process (clk)
begin
    if rising_edge(clk) then
        if button = '0' then
            status <= '1';
        else
            status <= '0';
        end if;
    end if;
end process;

The circuit generated by this code is:

Realize that the generated circuit will be only one flip-flop type D in which the input will be the denied value of button and the exit will be status. If you do the simulation, you will see that the value of status will always be '1' while button for '0' (pressed), where transitions of status shall be synchronous in relation to clk due to the registrar.

Notice that the sign status is amended to '1' only in the positive transition of clk after button be in '0' precisely because it is synchronous in relation to clk. The same happens at the end, when status is amended to 0.

Notes:

1. I considered that the button is pressed as logical level 0 because this is the most common implementation on development boards (circuit pull-down).

Answer 2

The problem is not in the syntax of if/else and yes on the comparison operator <= you are using in place of the assignment operator :=, how about:

if rising_edge(clk) then
   status := '1';
else 
   status := '0';
end if;